Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

--
-- This state machine recognizes the regular language
-- (0|1)*1101
--

entity reglang is
   port (
      clk 	: in std_logic;
      rst 	: in std_logic;
      Input : in std_logic;
		Output: out std_logic;
   );
end reglang;


architecture behavioral of reglang is

constant START : std_logic_vector(4 downto 0) := "00001";
constant STA   : std_logic_vector(4 downto 0) := "00010";
constant STB   : std_logic_vector(4 downto 0) := "00100";
constant STC   : std_logic_vector(4 downto 0) := "01000";
constant STD   : std_logic_vector(4 downto 0) := "10000";
constant DONTCARE   : std_logic_vector(4 downto 0) := "XXXXX";

signal State : std_logic_vector (4 downto 0);
signal NextState : std_logic_vector (4 downto 0);

begin

Output <= State(4); -- State D is a final state

process(clk, rst)
   begin
      if (rst = '1') then
         State <= START;
      elsif (clk'event and clk = '1') then
         State <= NextState;
      end if;
   end process;

process(State, Input)
	begin
	case State is
		when START =>
			if input = 1 then
				NextState <= STA;
			else 
				NextState <= START;
			endif;
		when STA =>
			if input = 1 then
				NextState <= STB;
			else 
				NextState <= START;
			endif;
		when STB =>
			if input = 0 then
				NextState <= STC;
			else 
				NextState <= STA;
			endif;
		when STC =>
			if input = 1 then
				NextState <= STD;
			else 
				NextState <= START;
			endif;
		when STD =>
			if input = 1 then
				NextState <= STB;
			else 
				NextState <= START;
			endif;
		when others =>
			NextState <= DONTCARE;
	end case;
	end process;

end behavioral;