Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity fifo is
   port (
      clk 	: in std_logic;
      rst 	: in std_logic;
      wr 	: in std_logic;
      rd 	: in std_logic;
      din 	: in std_logic_vector(7 downto 0);
		ff	: out std_logic;
		af	: out std_logic;
		ae	: out std_logic;
		ef	: out std_logic;
      dout : out std_logic_vector(7 downto 0)

   );
end fifo;


architecture behavioral of fifo is

signal head : std_logic_vector (3 downto 0);
signal tail : std_logic_vector (3 downto 0);
signal count : std_logic_vector (4 downto 0);
type MEM16x16 is array (0 to 15) of std_logic_vector(7 downto 0);
signal int_mem : MEM16x16;

begin

dout <= int_mem(CONV_INTEGER(tail));
ff <= '1' when (count = "10000" and (not (wr = '0' and rd = '1'))) or 
					(count = "01111" and wr = '1' and rd = '0') else '0';
af <= '1' when count > "01100" or 
					(count = "01100" and (not (wr = '0' and rd = '1'))) or
					(count = "01011" and wr = '1' and rd = '0') else '0';
ae <= '1' when count < "00100" or 
					(count = "00100" and (not (wr = '1' and rd = '0'))) or
					(count = "00101" and wr = '0' and rd = '1') else '0';
ef <= '1' when (count = "00000" and (not (wr = '1' and rd = '0'))) or 
					(count = "00001" and wr = '0' and rd = '1') else '0';


process(clk)
   begin
		if (clk'event and clk = '1') then
			if (wr = '1') then
				int_mem(CONV_INTEGER(head))(7 downto 0)  <= din;
			end if;
		end if;
	end process;

process(clk, rst)
   begin
      if (rst = '1') then
         head <= "0000";
      elsif (clk'event and clk = '1') then
         if(wr = '1') then
            head <= head + "0001";
         end if;
      end if;
   end process;

process(clk, rst)
   begin
      if (rst = '1') then
         tail <= "0000";
      elsif (clk'event and clk = '1') then
         if(rd = '1') then
            tail <= tail + "0001";
         end if;
      end if;
   end process;

process(clk, rst)
   begin
      if (rst = '1') then
         count <= "00000";
      elsif (clk'event and clk = '1') then
         if(wr = '1' and rd = '0') then
            count <= count + "00001";
			elsif(rd = '1' and wr = '0') then
            count <= count - "00001";
         end if;
      end if;
   end process;


end behavioral;