Library IEEE;
use IEEE.std_logic_1164.all;

--PRAGMA translate_off
library unisim;
use unisim.VCOMPONENTS.all;
--PRAGMA translate_on

entity dp_ram is
	generic ( 
		WIDTH			: INTEGER := 32
	);
	port (
		clk			: in	std_logic;
		write			: in	std_logic;
		wr_addr		: in	std_logic_vector(3 downto 0);
		wr_data_in	: in	std_logic_vector(WIDTH - 1 downto 0);
		wr_data_out	: out	std_logic_vector(WIDTH - 1 downto 0);
		rd_addr		: in	std_logic_vector(3 downto 0);
		rd_data		: out	std_logic_vector(WIDTH - 1 downto 0)
	);
end dp_ram;

architecture behavior of dp_ram is

	component RAM16X1D
		port (
			D     : in std_logic;
			WE    : in std_logic;
			WCLK  : in std_logic;
			A0    : in std_logic;
			A1    : in std_logic;
			A2    : in std_logic;
			A3    : in std_logic;
			DPRA0 : in std_logic;
			DPRA1 : in std_logic;
			DPRA2 : in std_logic;
			DPRA3 : in std_logic;
			SPO   : out std_logic;
			DPO   : out std_logic
		);
	end component;

begin

	LUTRAM_GENERATE_LOOP: for i in 0 to WIDTH-1 generate
		LUTRAM: RAM16X1D
			port map (
				D     => wr_data_in(i),
				WE    => write,
				WCLK  => clk,
				A0    => wr_addr(0),
				A1    => wr_addr(1),
				A2    => wr_addr(2),
				A3    => wr_addr(3),
				DPRA0 => rd_addr(0),
				DPRA1 => rd_addr(1),
				DPRA2 => rd_addr(2),
				DPRA3 => rd_addr(3),
				SPO   => wr_data_out(i),
				DPO   => rd_data(i));
	end generate LUTRAM_GENERATE_LOOP;

end behavior;