ECE 893 Fall 97 Reconfigurable Computing Topic List
Device Architectures
- Run-Time Reconfiguration 9/5/97 - Scott McMillan
- Wormhole Run-time Reconfiguration
- Computing Kernels Implemented with a Wormhole RTR CCM
- Incremental Reconfiguration for Pipelined Applications
- The RaPiD Architecture 9/19/97 - Greg Monn
- Mapping Applications to the RaPiD Configurable Architecture
- Issues in Processor - Configurable Logic Integration
9/26/97
- On the Viability of FPGA-Based Integrated Coprocessors
- A Quantitative Analysis of Processor - Programmable Logic
Interface
- Implementations of Processor - Configurable Logic
Integration 10/3/97
- Garp: A MIPS Processor with a Reconfigurable Coprocessor
- The Chimaera Reconfigurable Functional Unit
- A self-reconfiguring processor
Precision Issues
- Precision Issues 10/10/97 - Fred Stivers
- An Assessment of the Suitability of FPGA-Based Systems for
use in Digital Signal Processing
- Quantitative Analysis of Floating Point Arithmetic on FPGA
Based Custom Computing Machines
- Implementation of IEEE Single Precision Floating Point
Addition and Multiplication on FPGAs
System Architectures
- Splash 2 10/17/97
- The Splash 2 software environment
- VHDL Programming on Splash 2
- Other Architectures 10/24/97
- Virtual Computing and The Virtual Computer
- Teramac - Configurable Custom Computing
- A MOdular and Reprogrammable Real-time Processing Hardware,
MORRPH
Design Tools/Methodologies
- DISC 10/31/97 - Brian Boysen
- A Dynamic Instruction Set Computer
- DISC: The dynamic instruction set computer
- Supporting FPGA Microprocessors through Retargetable
Software Tools
- Data Parallel C Compilation 11/7/97 - Jeff Fann
- High Level Compilation for Fine Grained FPGAs
- FPGA Computing in a Data Parallel C
- Transmogrifier-2 Hardware and Software 11/14/97 - Matt Cettei
- The Transmogrifier-2: A 1 Million Gate Rapid Prototyping
System
- The Transmogrifier C Hardware Description Language and
Compiler for FPGAs
- High Level Programming Language Compilation I
11/21/97 - Rob Ross
- Scheduling and Partitioning ANSI-C Programs onto
Multi-FPGA CCM Architectures
- A Data-Parallel Programming Model for Reconfigurable
Architectures
- High Level Programming Language Compilation II 12/4/97
- SOP: A Reconfigurable Massively Parallel System and
Its Control-Data-Flow based Compiling Method
- C to VHDL Converter in a Codesign Environment
- Mathematics of Arrays
- An FPGA Based Reconfigurable Coprocessor Board
Utilizing Intelligent Data Prefetching
- Hardware Assists for High Performance Computing
Using Mathematics of Arrays